DATE '99 Proceedings of the conference on Design, automation and test in Europe
A temporal bipartitioning algorithm for dynamically reconfigurable FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
A framework for reconfigurable computing: task scheduling and context management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Synthesis and Optimization of Digital Circuits
Synthesis and Optimization of Digital Circuits
High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Performance-Oriented Fully Routable Dynamic Architecture for a Field
Performance-Oriented Fully Routable Dynamic Architecture for a Field
Reconfigurable architectures for general-purpose computing
Reconfigurable architectures for general-purpose computing
Self-Adaptive Networked Entities for Building Pervasive Computing Architectures
ICES '08 Proceedings of the 8th international conference on Evolvable Systems: From Biology to Hardware
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This paper presents a high-level temporal partitioning algorithm, which is able to split the VHDL description of a digital system into two equivalent subdescriptions. The primary goal of the algorithm is to obtain two area-balanced, time-independent partitions. The descriptions of these partitions can be separately simulated, synthesized and implemented as different configurations of a dynamically reconfigurable device. The partitioning principle is based on a directed task hypergraph. Each vertex of this hypergraph corresponds to one concurrent assignment of the description being analysed. The resources required for the physical implementation of each vertex are calculated by means of a simplified resource estimator. Time dependencies between vertices are denoted by hyperedges representing signals connecting appropriate concurrent assignments.