IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Image and Video Compression Standards: Algorithms and Architectures
Image and Video Compression Standards: Algorithms and Architectures
High-Level Partitioning of Digital Systems Based on Dynamically Reconfigurable Devices
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Generic Design Space Exploration for Reconfigurable Architectures
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Architectural synthesis of fixed-point DSP datapaths using FPGAs
International Journal of Reconfigurable Computing - Special issue on selected papers from ReConFig 2008
Power, performance and security optimized hardware design for H.264
Proceedings of the Sixth Annual Workshop on Cyber Security and Information Intelligence Research
Design space exploration for low-power reconfigurable fabrics
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
Accurate Area, Time and Power Models for FPGA-Based Implementations
Journal of Signal Processing Systems
An analytical model for multilevel performance prediction of Multi-FPGA systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Quipu: A Statistical Model for Predicting Hardware Resources
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Field-programmable gate arrays (FPGAs) have become increasingly interesting in system design and due to the rapid technological progress ever larger devices are commercially affordable. These trends make FPGAs an alternative in application areas where extensive data processing plays an important role. Consequently, the desire emerges for early performance estimation in order to quantify the FPGA approach and to compare it with traditional alternatives. In this paper, we propose a high-level estimation methodology for area and performance parameters of regular FPGA designs to be found in multimedia, telecommunications or cryptography. The goal is to provide a means that allows early quantification of an FPGA design and that enables early trade-off considerations. We present our estimation approach as well as evaluation results, which are based on several implemented applications and prove the suitability of the proposed estimation approach.