A Computational Approach to Edge Detection
IEEE Transactions on Pattern Analysis and Machine Intelligence
An Entropy-Based Measure of Software Complexity
IEEE Transactions on Software Engineering - Special issue on software measurement principles, techniques, and environments
Essence of Neural Networks
Software Engineering Measurement
Software Engineering Measurement
Workload Design: Selecting Representative Program-Input Pairs
Proceedings of the 2002 International Conference on Parallel Architectures and Compilation Techniques
High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Using estimates from behavioral synthesis tools in compiler-directed design space exploration
Proceedings of the 40th annual Design Automation Conference
A MATLAB Compiler for Distributed, Heterogeneous, Reconfigurable Computing Systems
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Characteristic program complexity measures
ICSE '84 Proceedings of the 7th international conference on Software engineering
SPARK: A High-Lev l Synthesis Framework For Applying Parallelizing Compiler Transformations
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
MELP: The New Federal Standard at 2400 Bps
ICASSP '97 Proceedings of the 1997 IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP '97)-Volume 2 - Volume 2
Accurate Area and Delay Estimators for FPGAs
Proceedings of the conference on Design, automation and test in Europe
An area estimation methodology for FPGA based designs at systemc-level
Proceedings of the 41st annual Design Automation Conference
Compile-time area estimation for LUT-based FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Software Engineering
Cell broadband engine architecture and its first implementation: a performance view
IBM Journal of Research and Development
Area-Time Estimation of Controller for Porting C-Based Functions onto FPGA
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
A study of cross-validation and bootstrap for accuracy estimation and model selection
IJCAI'95 Proceedings of the 14th international joint conference on Artificial intelligence - Volume 2
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Designing Modular Hardware Accelerators in C with ROCCC 2.0
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Information and Software Technology
Automatic memory partitioning: increasing memory parallelism via data structure partitioning
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Early Prediction of Hardware Complexity in HLL-to-HDL Translation
FPL '10 Proceedings of the 2010 International Conference on Field Programmable Logic and Applications
LegUp: high-level synthesis for FPGA-based processor/accelerator systems
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Modern Applied Statistics with S
Modern Applied Statistics with S
Pruning hardware evaluation space via correlation-driven application similarity analysis
Proceedings of the 8th ACM International Conference on Computing Frontiers
High Level Power Estimation Models for FPGAs
ISVLSI '11 Proceedings of the 2011 IEEE Computer Society Annual Symposium on VLSI
The q2 profiling framework: driving application mapping for heterogeneous reconfigurable platforms
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Design Space Pruning Through Early Estimations of Area/Delay Tradeoffs for FPGA Implementations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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There has been a steady increase in the utilization of heterogeneous architectures to tackle the growing need for computing performance and low-power systems. The execution of computation-intensive functions on specialized hardware enables to achieve substantial speedups and power savings. However, with a large legacy code base and software engineering experts, it is not at all obvious how to easily utilize these new architectures. As a result, there is a need for comprehensive tool support to bridge the knowledge gap of many engineers as well as to retarget legacy code. In this article, we present the Quipu modeling approach, which consists of a set of tools and a modeling methodology that can generate hardware estimation models, which provide valuable information for developers. This information helps to focus their efforts, to partition their application, and to select the right heterogeneous components. We present Quipu’s capability to generate domain-specific models, that are up to several times more accurate within their particular domain (error: 4.6%) as compared to domain-agnostic models (error: 23%). Finally, we show how Quipu can generate models for a new toolchain and platform within a few days.