A VLIW architecture for a trace scheduling compiler
ASPLOS II Proceedings of the second international conference on Architectual support for programming languages and operating systems
A high-performance microarchitecture with hardware-programmable functional units
MICRO 27 Proceedings of the 27th annual international symposium on Microarchitecture
Spert-II: A Vector Microprocessor System
Computer - Special issue: neural computing: companion issue to Spring 1996 IEEE Computational Science & Engineering
Sequencing run-time reconfigured hardware with software
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Communications of the ACM
Parallel algorithms for regular architectures: meshes and pyramids
Parallel algorithms for regular architectures: meshes and pyramids
Signal processing at 250 MHz using high-performance FPGA's
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Managing pipeline-reconfigurable FPGAs
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Communications of the ACM - Special issue on computer architecture
Pipeline morphing and virtual pipelines
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
The Chimaera reconfigurable functional unit
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
The Design and Implementation of a Context Switching FPGA
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
The NAPA Adaptive Processing Architecture
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
Performance-Oriented Fully Routable Dynamic Architecture for a Field
Performance-Oriented Fully Routable Dynamic Architecture for a Field
Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor
Proceedings of the 31st annual international symposium on Computer architecture
On the implementation of virtual array using configuration plane
APPT'07 Proceedings of the 7th international conference on Advanced parallel processing technologies
Synchroscalar: initial lessons in power-aware design of a tile-based embedded architecture
PACS'03 Proceedings of the Third international conference on Power - Aware Computer Systems
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While reconfigurable computing promises to deliverincomparable performance, it is still a marginal technology due tothe high cost of developing and upgrading applications. Hardwarevirtualization can be used to significantly reduce both these costs.In this paper we describe the benefits of hardware virtualization,and show how it can be achieved using the technique of pipelinereconfiguration. The result is PipeRench, an architecture thatsupports robust compilation and provides forward compatibility. Ourpreliminary performance analysis on PipeRench predicts that it willoutperform commercial FPGAs and DSPs in both overall performance andin performance normalized for silicon area over a broad range ofproblem sizes.