Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
MIPS RISC architectures
The Ring Array Processor: a multiprocessing peripheral for connectionist applications
Journal of Parallel and Distributed Computing - Special issue on neural computing on massively parallel processing
Very Long Instruction Word architectures and the ELI-512
ISCA '83 Proceedings of the 10th annual international symposium on Computer architecture
Initial results on the performance and cost of vector microprocessors
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Simple vector microprocessors for multimedia applications
MICRO 31 Proceedings of the 31st annual ACM/IEEE international symposium on Microarchitecture
PipeRench: a co/processor for streaming multimedia acceleration
ISCA '99 Proceedings of the 26th annual international symposium on Computer architecture
Vector instruction set support for conditional operations
Proceedings of the 27th annual international symposium on Computer architecture
Journal of VLSI Signal Processing Systems - Special issue on VLSI on custom computing technology
Efficient conditional operations for data-parallel architectures
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Tarantula: a vector extension to the alpha architecture
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
Imagine: Media Processing with Streams
IEEE Micro
Exploring the VLSI Scalability of Stream Processors
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Efficient Place and Route for Pipeline Reconfigurable Architectures
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
The Vector-Thread Architecture
Proceedings of the 31st annual international symposium on Computer architecture
The Vector-Thread Architecture
IEEE Micro
Low-error, High-speed Approximation of the Sigmoid Function for Large FPGA Implementations
Journal of Signal Processing Systems
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfiguration support for vector operations
International Journal of High Performance Systems Architecture
Exploring the tradeoffs between programmability and efficiency in data-parallel accelerators
Proceedings of the 38th annual international symposium on Computer architecture
Exploring the Tradeoffs between Programmability and Efficiency in Data-Parallel Accelerators
ACM Transactions on Computer Systems (TOCS)
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Spert-II is a high-performance system for signal processing, multimedia, and neural network applications. The system is based on a custom fixed-point vector microprocessor packaged for standard workstations. The microprocessor is a single-chip implementation of the Torrent vector instruction-set architecture.Spert-II includes a versatile set of library routines. It also has a programming environment much like that of a workstation.The authors used the system to accelerate neural net algorithms. When they employed Spert-II to perform training and recall for the neural networks they use in speech recognition research, it proved to be faster than commercial workstations.