The Vector-Thread Architecture

Authors:
Ronny Krashinsky;Christopher Batten;Mark Hampton;Steve Gerding;Brian Pharris;Jared Casper;Krste Asanovic
Affiliations:
Massachusetts Institute of Technology;Massachusetts Institute of Technology;Massachusetts Institute of Technology;Massachusetts Institute of Technology;Massachusetts Institute of Technology;Massachusetts Institute of Technology;Massachusetts Institute of Technology
Venue:
IEEE Micro
Year:
2004

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Abstract

The vector-thread (VT) architecture supports a seamless intermingling of vector and multithreadedcomputation to flexibly and compactly encode application parallelism and locality. VT processors exploit this encoding to provide high performance with low power and small area.