RAPANUI: rapid prototyping for media processor architecture exploration

Authors:
Guillermo Payá Vayá;Javier Martín Langerwerf;Peter Pirsch
Affiliations:
Institute of Microelectronic Systems, University of Hannover, Hannover, Germany;Institute of Microelectronic Systems, University of Hannover, Hannover, Germany;Institute of Microelectronic Systems, University of Hannover, Hannover, Germany
Venue:
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Year:
2005

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Abstract

This paper describes a new rapid prototyping-based design framework for exploring and validating complex multiprocessor architectures for multimedia applications. The new methodology combines a typical ASIC flow with an FPGA flow focused on rapid prototyping. In order to make an exhaustive verification of the system architecture, a reference model that specifies the hardware implementation is used for validating both, HDL description and emulated system. Functional coverage in addition to traditional code coverage is used to test 100% of data, control and structural hazards of the system architecture. The reference model is also part of a stand-alone simulation environment. This allows hardware and application development be supported by a unique system model.