A Design and Tool Reuse Methodology for Rapid Prototyping of Application Specific Instruction Set Processors

Authors:
Young Geol Kim;Tag Gon Kim
Affiliations:
-;-
Venue:
RSP '99 Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping
Year:
1999

Citing 0
Cited 3

High-level modeling and FPGA prototyping of microprocessors

FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Trace-driven rapid pipeline architecture evaluation scheme for ASIP design

ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
RAPANUI: rapid prototyping for media processor architecture exploration

SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation

Quantified Score

Hi-index	0.00

Visualization

Abstract

This paper proposes a design and tool reuse schemes for a rapid prototyping of application specific instruction-set processors (ASIP). We propose a three-level hierarchical architecture abstraction method for top-down processor design. We also propose a reusable architecture descrip-tion language (READ) and a family of retargetable simulators that allow a top-down processor description and prototyping from instruction-set design to RTL implementation.