Analog VLSI and neural systems
Analog VLSI and neural systems
Wiring considerations in analog VLSI systems, with application to field-programmable networks
Wiring considerations in analog VLSI systems, with application to field-programmable networks
VLSI analogs of neuronal visual processing: a synthesis of form and function
VLSI analogs of neuronal visual processing: a synthesis of form and function
Analog VLSI neuromorphic image acquisition and pre-processing systems
Neural Networks - Special issue: automatic target recognition
Spert-II: A Vector Microprocessor System
Computer - Special issue: neural computing: companion issue to Spring 1996 IEEE Computational Science & Engineering
Digital VLSI for neural networks
The handbook of brain theory and neural networks
Analog VLSI-based modeling of the primate oculomotor system
Neural Computation
Introduction to VLSI Systems
The computer and the brain
Energy-efficient coding with discrete stochastic events
Neural Computation
MICRONEURO '96 Proceedings of the 5th International Conference on Microelectronics for Neural Networks and Fuzzy Systems
Synaptic Dynamics in Analog VLSI
Neural Computation
CMOL: Second life for silicon?
Microelectronics Journal
Validity of the single processor approach to achieving large scale computing capabilities
AFIPS '67 (Spring) Proceedings of the April 18-20, 1967, spring joint computer conference
A Delay-Insensitive Address-Event Link
ASYNC '09 Proceedings of the 2009 15th IEEE Symposium on Asynchronous Circuits and Systems (async 2009)
Embedded DRAM: technology platform for the Blue Gene/L chip
IBM Journal of Research and Development
FPGA Implementation of Izhikevich Spiking Neural Networks for Character Recognition
RECONFIG '09 Proceedings of the 2009 International Conference on Reconfigurable Computing and FPGAs
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
Real-time simulation of biologically realistic stochastic neurons in VLSI
IEEE Transactions on Neural Networks
Emulating Mammalian Vision on Reconfigurable Hardware
FCCM '12 Proceedings of the 2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines
IEEE Transactions on Computers
Pulse-stream VLSI neural networks mixing analog and digital techniques
IEEE Transactions on Neural Networks
IEEE Transactions on Neural Networks
Simple model of spiking neurons
IEEE Transactions on Neural Networks
Which model to use for cortical spiking neurons?
IEEE Transactions on Neural Networks
Synchrony detection and amplification by silicon neurons with STDP synapses
IEEE Transactions on Neural Networks
IEEE Transactions on Neural Networks
IEEE Transactions on Neural Networks
The design of a neuro-microprocessor
IEEE Transactions on Neural Networks
A Digital Neurosynaptic Core Using Event-Driven QDI Circuits
ASYNC '12 Proceedings of the 2012 18th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)
Compass: a scalable simulator for an architecture for cognitive computing
SC '12 Proceedings of the International Conference on High Performance Computing, Networking, Storage and Analysis
ICANN'12 Proceedings of the 22nd international conference on Artificial Neural Networks and Machine Learning - Volume Part I
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We present a design framework for neuromorphic architectures in the nano-CMOS era. Our approach to the design of spiking neurons and STDP learning circuits relies on parallel computational structures where neurons are abstracted as digital arithmetic logic units and communication processors. Using this approach, we have developed arrays of silicon neurons that scale to millions of neurons in a single state-of-the-art Field Programmable Gate Array (FPGA). We demonstrate the validity of the design methodology through the implementation of cortical development in a circuit of spiking neurons, STDP synapses, and neural architecture optimization.