The design of a neuro-microprocessor

Authors:
J. Wawrzynek;K. Asanovic;N. Morgan
Affiliations:
California Univ., Berkeley, CA;-;-
Venue:
IEEE Transactions on Neural Networks
Year:
1993

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Abstract

The architecture of a neuro-microprocessor is presented. This processor was designed using the results of careful analysis of a set of applications and extensive simulation of moderate-precision arithmetic for back-propagation networks. Simulated performance results and test-chip results for the processor are presented. This work is an important intermediate step in the development of a connectionist network supercomputer