An On-Chip Adaptive Spike Timing Based Offset Cancellation Scheme for Neuromorphic Sensing
AHS '07 Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems
A programmable time event coded circuit block for reconfigurable neuromorphic computing
IWANN'07 Proceedings of the 9th international work conference on Artificial neural networks
Synchrony detection and amplification by silicon neurons with STDP synapses
IEEE Transactions on Neural Networks
Real-time computing platform for spiking neurons (RT-spike)
IEEE Transactions on Neural Networks
Dynamically Reconfigurable Silicon Array of Spiking Neurons With Conductance-Based Synapses
IEEE Transactions on Neural Networks
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A generic programmable spike-timing based circuit which forms the building block of a reconfigurable neuromorphic array is implemented in analog VLSI. An array of programmable spike time event coded circuit blocks is configured to implement functional circuit blocks of a spike time based neuromorphic model. A reconfigurable neuromorphic array chip with 10 event blocks is fabricated using Austria Microsystems 0.35@mm CMOS technology to demonstrate the functionality of the circuits in silicon.