Analog VLSI and neural systems
Analog VLSI and neural systems
Wiring considerations in analog VLSI systems, with application to field-programmable networks
Wiring considerations in analog VLSI systems, with application to field-programmable networks
A pulse-coded communications infrastructure for neuromorphic systems
Pulsed neural networks
Analog VLSI-based modeling of the primate oculomotor system
Neural Computation
An Analog VLSI System for Stereoscopic Vision
An Analog VLSI System for Stereoscopic Vision
Biophysiologically plausible implementations of the maximum operation
Neural Computation
Multi-Chip Neuromorphic Motion Processing
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Biophysics of Computation: Information Processing in Single Neurons (Computational Neuroscience Series)
Theoretical Neuroscience: Computational and Mathematical Modeling of Neural Systems
Theoretical Neuroscience: Computational and Mathematical Modeling of Neural Systems
Test infrastructure for address-event-representation communications
IWANN'05 Proceedings of the 8th international conference on Artificial Neural Networks: computational Intelligence and Bioinspired Systems
Real-time computing platform for spiking neurons (RT-spike)
IEEE Transactions on Neural Networks
Dynamically Reconfigurable Silicon Array of Spiking Neurons With Conductance-Based Synapses
IEEE Transactions on Neural Networks
Computation with spikes in a winner-take-all network
Neural Computation
Efficient simulation of large-scale spiking neural networks using CUDA graphics processors
IJCNN'09 Proceedings of the 2009 international joint conference on Neural Networks
A hierachical configuration system for a massively parallel neural hardware platform
Proceedings of the 9th conference on Computing Frontiers
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We present a multichip, mixed-signal VLSI system for spike-based vision processing. The system consists of an 80 × 60 pixel neuromorphic retina and a 4800 neuron silicon cortex with 4,194,304 synapses. Its functionality is illustrated with experimental data on multiple components of an attention-based hierarchical model of cortical object recognition, including feature coding, salience detection, and foveation. This model exploits arbitrary and reconfigurable connectivity between cells in the multichip architecture, achieved by asynchronously routing neural spike events within and between chips according to a memory-based look-up table. Synaptic parameters, including conductance and reversal potential, are also stored in memory and are used to dynamically configure synapse circuits within the silicon neurons.