Embedded DRAM: technology platform for the Blue Gene/L chip

  • Authors:

  • S. S. Iyer;J. E. Barth;P. C. Parries;J. P. Norum;J. P. Rice;L. R. Logan;D. Hoyniak

  • Affiliations:

  • IBM Systems and Technology Group, Hopewell Junction, New York;IBM Systems and Technology Group, Essex Junction Development Laboratory, Essex Junction, Vermont;IBM Systems and Technology Group, Hopewell Junction, New York;IBM Systems and Technology Group, Hopewell Junction, New York;IBM Systems and Technology Group, Hopewell Junction, New York;IBM Systems and Technology Group, Hopewell Junction, New York;IBM Systems and Technology Group, Hopewell Junction, New York

  • Venue:
  • IBM Journal of Research and Development
  • Year:
  • 2005

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Abstract

The Blue Gene®/L chip is a technological tour de force that embodies the system-on-a-chip concept in its entirety. This paper outlines the salient features of this 130-nm complementary metal oxide semiconductor (CMOS) technology, including the IBM unique embedded dynamic random access memory (DRAM) technology. Crucial to the execution of Blue Gene/L is the simultaneous instantiation of multiple PowerPC® cores, high-performance static random access memory (SRAM), DRAM, and several other logic design blocks on a single-platform technology. The IBM embedded DRAM platform allows this seamless integration without compromising performance, reliability, or yield. We discuss the process architecture, the key parameters of the logic components used in the processor cores and other logic design blocks, the SRAM features used in the L2 cache, and the embedded DRAM that forms the L3 cache. We also discuss the evolution of embedded DRAM technology into a higher-performance space in the 90-nm and 65-nm nodes and the potential for dynamic memory to improve overall memory subsystem performance.