Stress induced dislocations in silicon integrated circuits
IBM Journal of Research and Development
Dynamic Memory Design for Low Data-Retention Power
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Effects of Bit Line Coupling on the Faulty Behavior of DRAMs
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Space of DRAM fault models and corresponding testing
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Challenges and future directions for the scaling of dynamic random-access memory (DRAM)
IBM Journal of Research and Development
Embedded DRAM: technology platform for the Blue Gene/L chip
IBM Journal of Research and Development
Block-based multiperiod dynamic memory design for low data-retention power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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