Dynamic Memory Design for Low Data-Retention Power

• Authors: Joohee Kim;Marios C. Papaefthymiou
• Venue: PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
• Year: 2000

The emergence of data-intensive applications in mobile environments has resulted in portable electronic systems with increasingly large dynamic memories. The typical operating pattern exhibited by these applications is a relatively short burst of operations followed by longer periods of standby. Due to their periodic refresh requirements, dynamic memories consume substantial power even during standby and thus have a significant impact on battery lifetime. In this paper we investigate a methodology for designing dynamic memory with low data-retention power. Our approach relies on the fact that the refresh period of a memory array is dictated by only a few, worst-case leaky cells. In our scheme, multiple refresh periods are used to reduce energy dissipation by selectively refreshing only the cells that are about to lose their stored values. Additional energy savings are achieved by using error-correction to restore corrupted cell values and thus allow for extended refresh periods. We describe an exact O(nk-1)-time algorithm that, given a memory array with n refresh blocks and two positive integers k and l, computes k refresh periods that maximize the average refresh period of a memory array when refreshing occurs in blocks of l cells. In simulations with 16Mb memory arrays and a (72, 64) modified Hamming single-error correction code, our scheme results in an average refresh period of up to 11 times longer than the original refresh period.