The evolution of IBM CMOS DRAM technology
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Optimizing the DRAM refresh count for merged DRAM/logic LSIs
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Dynamic Memory Design for Low Data-Retention Power
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Fault-Tolerant Refresh Power Reduction of DRAMs for Quasi-Nonvolatile Data Retention
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Frame Buffer Energy Optimization by Pixel Prediction
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Reducing cache power with low-cost, multi-bit error-correcting codes
Proceedings of the 37th annual international symposium on Computer architecture
Flikker: saving DRAM refresh-power through critical data partitioning
Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems
Power management of hybrid DRAM/PRAM-based main memory
Proceedings of the 48th Design Automation Conference
Energy-Efficient value-based selective refresh for embedded DRAMs
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
RAIDR: Retention-Aware Intelligent DRAM Refresh
Proceedings of the 39th Annual International Symposium on Computer Architecture
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Dynamic random access memorys (DRAMs) are widely used in portable applications due to their high storage density. In standby mode, the main source of DRAM power dissipation is the refresh operation that periodically restores leaking charge in each memory cell to its correct level. Conventional DRAMs use a single refresh period determined by the cell with the largest leakage. This approach is simple but dissipative, because it forces unnecessary refreshes for the majority of the cells with small leakage. In this paper, we investigate a novel scheme that relies on small refresh blocks and multiple refresh periods to reduce DRAM dissipation by decreasing the number of cells refreshed too often. In contrast to conventional row-based refresh, small refresh blocks are used to increase worst case data retention times. Long periods are used to accommodate cells with small leakage. Retention times are further extended by adding a swap cell to each refresh block. We give a novel polynomial-time algorithm for computing an optimal set of refresh periods for block-based multiperiod refresh. Specifically, given an integer K and a distribution of data-retention times, in O(KN2) steps our algorithm computes Krefresh periods that minimize DRAM dissipation, where N is the number of refresh blocks in the memory. We describe and evaluate a scalable implementation of our refresh scheme whose overhead is asymptotically linear with memory size. In simulations with a 16-Mb DRAM, block-based multiperiod refresh reduces DRAM standby dissipation by a multiplicative factor of 4 with area overhead below 6%. Moreover, our proposed scheme is robust to semiconductor process variations, with power savings degrading no more than 7% over a 20-fold increase of leaky cells.