MediaBench: a tool for evaluating and synthesizing multimedia and communicatons systems
MICRO 30 Proceedings of the 30th annual ACM/IEEE international symposium on Microarchitecture
Optimizing the DRAM refresh count for merged DRAM/logic LSIs
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Dynamic zero compression for cache energy reduction
Proceedings of the 33rd annual ACM/IEEE international symposium on Microarchitecture
Frequent value locality and value-centric data cache design
ASPLOS IX Proceedings of the ninth international conference on Architectural support for programming languages and operating systems
Hardware and Software Techniques for Controlling DRAM Power Modes
IEEE Transactions on Computers
Value-Conscious Cache: Simple Technique for Reducing Cache Access Power
Proceedings of the conference on Design, automation and test in Europe - Volume 1
A low-power graphics LSI integrating 29Mb embedded DRAM for mobile multimedia applications
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Block-based multiperiod dynamic memory design for low data-retention power
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Flikker: saving DRAM refresh-power through critical data partitioning
Proceedings of the sixteenth international conference on Architectural support for programming languages and operating systems
A survey of architectural techniques for DRAM power management
International Journal of High Performance Systems Architecture
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DRAM idle power consumption consists for a large part of the power required for the refresh operation. This is exacerbated by (i) increasing amount of memory devoted to cache, that filter out many accesses to DRAM, and (ii) increased temperature of the chips, which increase leakage and thus data retention times. The well-known structured distribution of zeros in a memory, combined with the observation that cells containing zeros in a DRAM do not require to be refreshed, can be constructively used together to reduce the unnecessary number of required refresh operations. We propose a value-based selective refresh scheme in which both horizontal and vertical clusters of zeros are identified and used to selectively deactivated refresh of such clusters. As a result, our technique significantly achieves a net reduction of the number of refresh operations on average of 31%, evaluated on a set of typical embedded applications.