Optimizing the DRAM refresh count for merged DRAM/logic LSIs

Authors:
Taku Ohsawa;Koji Kai;Kazuaki Murakami
Affiliations:
Department of Computer Scince and Communication Engineering Kyushu University 6-1 Kasuga-Koen, Kasuga, Fukuoka, 816-8580, Japan;Institute of Systems & Information Technologies/KYUSHU, 2-1-22-707 Momochihama, Sawara-ku, Fukuoka 814-0001, Japan;Department of Computer Scince and Communication Engineering Kyushu University 6-1 Kasuga-Koen, Kasuga, Fukuoka, 816-8580, Japan
Venue:
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Year:
1998

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Abstract

In merged DRAM/logic LSIs, the DRAM portion could suffer from shorter data retention time because of heat and noise caused by the logic portion. Frequent refreshes increase power consumption. Also, they disturb normal DRAM accesses leading to performance degradation. In order to overcome this problem, we propose several DRAM refresh architectures. The basic idea is to eliminate unnecessary DRAM refreshes. We have estimated the DRAM refresh count in executing benchmark programs under several architecture models. As a result, in the most effective combination of the architectures, we have obtained more than 80% reduction against a conventional DRAM refresh architecture for most benchmark programs. In addition to it, even when we have taken normal DRAM access into account, we have obtained more than 50% reduction for several benchmarks.