Exhaustive and Near-Exhaustive Memory Testing Techniques and theirBIST Implementations
Journal of Electronic Testing: Theory and Applications
Optimizing the DRAM refresh count for merged DRAM/logic LSIs
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Dynamic Memory Design for Low Data-Retention Power
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
An Investigation into Crosstalk Noise in DRAM Structures
MTDT '02 Proceedings of the The 2002 IEEE International Workshop on Memory Technology, Design and Testing
DRAM Circuit Design: Fundamental and High-Speed Topics
DRAM Circuit Design: Fundamental and High-Speed Topics
Nanoscale Memory Repair
Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Influence of Bit-Line Coupling and Twisting on the Faulty Behavior of DRAMs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
RAIDR: Retention-Aware Intelligent DRAM Refresh
Proceedings of the 39th Annual International Symposium on Computer Architecture
NVM duet: unified working memory and persistent store architecture
Proceedings of the 19th international conference on Architectural support for programming languages and operating systems
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DRAM cells store data in the form of charge on a capacitor. This charge leaks off over time, eventually causing data to be lost. To prevent this data loss from occurring, DRAM cells must be periodically refreshed. Unfortunately, DRAM refresh operations waste energy and also degrade system performance by interfering with memory requests. These problems are expected to worsen as DRAM density increases. The amount of time that a DRAM cell can safely retain data without being refreshed is called the cell's retention time. In current systems, all DRAM cells are refreshed at the rate required to guarantee the integrity of the cell with the shortest retention time, resulting in unnecessary refreshes for cells with longer retention times. Prior work has proposed to reduce unnecessary refreshes by exploiting differences in retention time among DRAM cells; however, such mechanisms require knowledge of each cell's retention time. In this paper, we present a comprehensive quantitative study of retention behavior in modern DRAMs. Using a temperature-controlled FPGA-based testing platform, we collect retention time information from 248 commodity DDR3 DRAM chips from five major DRAM vendors. We observe two significant phenomena: data pattern dependence, where the retention time of each DRAM cell is significantly affected by the data stored in other DRAM cells, and variable retention time, where the retention time of some DRAM cells changes unpredictably over time. We discuss possible physical explanations for these phenomena, how their magnitude may be affected by DRAM technology scaling, and their ramifications for DRAM retention time profiling mechanisms.