Random Pattern Testing Versus Deterministic Testing of RAMs
IEEE Transactions on Computers
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Testing for Coupled Cells in Random-Access Memories
IEEE Transactions on Computers
Deterministic tests for detecting single V-coupling faults in RAMs
Journal of Electronic Testing: Theory and Applications
Transparent Memory Testing for Pattern-Sensitive Faults
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Pseudo-exhaustive word-oriented DRAM testing
EDTC '95 Proceedings of the 1995 European conference on Design and Test
BIST for Embedded Word-Oriented DRAM
MTDT '98 Proceedings of the 1998 IEEE International Workshop on Memory Technology, Design and Testing
Antirandom Test Vectors for BIST in Hardware/Software Systems
Fundamenta Informaticae
Automation and Remote Control
Proceedings of the 40th Annual International Symposium on Computer Architecture
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In this work we investigate the problem of detection and location ofsingle and unlinked multiple k-coupling faults in n × 1 random-access memories (RAMs). This fault model covers allcrosstalks between any k cells in n × 1 RAMs. The problem of memory testing has been reduced to the problem of the generationof (n,k-1)-exhaustive backgrounds. We have obtained practical test lengths, for a memory size around 1 M, for detecting up to6-couplings by exhaustive tests and up to 9-couplings bynear-exhaustive tests. The best known test algorithms up to nowprovide for the detection of 5-couplings only in a 1 M memory, usingexhaustive tests. Beyond these parameters, test lengths wereimpractical. Furthermore, our method for generation of(n,k-1)-exhaustive backgrounds yields short test lengths givingrise to considerably shorter testing times than the present mostefficient tests for large n and for k greater than 3. Our test lengths are 50% shorter than other methods for the case of detectingup to 5-couplings in a 1 Mbit RAM. The systematic nature of both ourtests enables us to use a built-in self-test (BIST) scheme, for RAMs, with low hardware overhead. For a 1Mbit memory, the BIST areaoverhead for the detection of 5-couplings is less than 1% for SRAMand 6.8% for a DRAM. For the detection of 9-couplings with 99% or higher probability, the BIST area overhead is less than 0.2% forSRAM and 1.5% for DRAM.