Fault Diagnosis of RAMs from Random Testing Experiments
IEEE Transactions on Computers
Functional testing vs. structural testing of RAMs
Fehlertolerierende Rechensysteme, 2. GI/NTG/GMR-Fachtagung
GI - 7. Jahrestagung, Nürnberg
Functional and pattern sensitive fault testing algorithms for semiconductor random access memories.
Functional and pattern sensitive fault testing algorithms for semiconductor random access memories.
Fault Diagnosis of RAMs from Random Testing Experiments
IEEE Transactions on Computers
Testing for Coupled Cells in Random-Access Memories
IEEE Transactions on Computers
Fault Coverage and Test Length Estimation for Random Pattern Testing
IEEE Transactions on Computers - Special issue on fault-tolerant computing
Testing for Bounded Faults in RAMs
Journal of Electronic Testing: Theory and Applications
Exhaustive and Near-Exhaustive Memory Testing Techniques and theirBIST Implementations
Journal of Electronic Testing: Theory and Applications
Symmetric transparent BIST for RAMs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Self-adjusting output data compression: an efficient BIST technique for RAMs
Proceedings of the conference on Design, automation and test in Europe
Industrial BIST of Embedded RAMs
IEEE Design & Test
Design of Cache Test Hardware on the HP PA8500
IEEE Design & Test
Efficient Online and Offline Testing of Embedded DRAMs
IEEE Transactions on Computers
Detection of CMOS address decoder open faults with March and pseudo random memory tests
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Error Detecting Refreshment for Embedded DRAMs
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
The Implementation of Pseudo-Random Memory Tests on Commercial Memory Testers
ITC '97 Proceedings of the 1997 IEEE International Test Conference
DESIGN OF CACHE TEST HARDWARE ON THE HP PA8500
ITC '97 Proceedings of the 1997 IEEE International Test Conference
| Hi-index | 14.99 |
The number of (random) patterns required for random testing of RAMs (random-access memories), when classical fault models including pattern-sensitive faults are considered is determined. Markov chains are a powerful tool for this purpose. Single faults are considered first, and the influence of different parameters is analyzed. Double faults are then considered and arguments are presented to extend the results to all multiple-coupling faults. Those results are compared to the optimal or best-known number of test patterns required when deterministic testing is considered, for the same fault models.