Built-In Testing of Memory Using an On-Chip Compact Testing Scheme
IEEE Transactions on Computers
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Error-control coding for computer systems
Error-control coding for computer systems
Random Pattern Testing Versus Deterministic Testing of RAMs
IEEE Transactions on Computers
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Realistic Built-In Self-Test for Static RAMs
IEEE Design & Test
Serial Interfacing for Embedded-Memory Testing
IEEE Design & Test
Testing a Switching Memory in a Telcommunication System
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Synthesized Transparent BIST for Detecting Scrambled Pattern-Sensitive Faults in RAMs
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation
Proceedings of the IEEE International Test Conference on Test and Design Validity
A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM
Proceedings of the IEEE International Test Conference on Test and Design Validity
Self-Learning Signature Analysis for Non-Volatile Memory Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Exact Aliasing Computation for RAM BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Symmetric transparent BIST for RAMs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Efficient Online and Offline Testing of Embedded DRAMs
IEEE Transactions on Computers
Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Error Detecting Refreshment for Embedded DRAMs
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
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After write operations, BIST schemes for RAMS relying on signature analysis must compress the entire memory contents to update the reference signature. This paper introduces a new scheme for output data compression which avoids this overhead while retaining the benefits of signature analysis. The proposed technique is based on a new memory characteristic derived as the modulo-2 sum of all addresses pointing to non-zero cells. This characteristic can be adjusted concurrently with write operations by simple EXOR-operations on the initial characteristic and on the addresses affected by the change.