Built-In Testing of Memory Using an On-Chip Compact Testing Scheme
IEEE Transactions on Computers
Built-in test for VLSI: pseudorandom techniques
Built-in test for VLSI: pseudorandom techniques
Error-control coding for computer systems
Error-control coding for computer systems
Random Pattern Testing Versus Deterministic Testing of RAMs
IEEE Transactions on Computers
Computer architecture: a quantitative approach
Computer architecture: a quantitative approach
IBM Journal of Research and Development
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Self-adjusting output data compression: an efficient BIST technique for RAMs
Proceedings of the conference on Design, automation and test in Europe
Embedded DRAM architectural trade-offs
Proceedings of the conference on Design, automation and test in Europe
Realistic Built-In Self-Test for Static RAMs
IEEE Design & Test
Serial Interfacing for Embedded-Memory Testing
IEEE Design & Test
Using March Tests to Test SRAMs
IEEE Design & Test
Integrating Online and Offline Testing of a Switching Memory
IEEE Design & Test
Testing a Switching Memory in a Telcommunication System
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Synthesized Transparent BIST for Detecting Scrambled Pattern-Sensitive Faults in RAMs
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
A BIST Methodology for Comprehensive Testing of RAM with Reduced Heat Dissipation
Proceedings of the IEEE International Test Conference on Test and Design Validity
A Built-In Self-Test Circuit with Timing Margin Test Function in a 1Gbit Synchronous DRAM
Proceedings of the IEEE International Test Conference on Test and Design Validity
Self-Learning Signature Analysis for Non-Volatile Memory Testing
Proceedings of the IEEE International Test Conference on Test and Design Validity
Proceedings of the IEEE International Test Conference on Discover the New World of Test and Design
Exact Aliasing Computation for RAM BIST
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
Error Detecting Refreshment for Embedded DRAMs
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
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This paper presents an integrated approach for both built-in online and offline testing of embedded DRAMs. It is based on a new technique for output data compression which offers the same benefits as signature analysis during offline test, but also supports efficient online consistency checking. The initial fault-free memory contents are compressed to a reference characteristic and compared to test characteristics periodically. The reference characteristic depends on the memory contents, but unlike similar characteristics based on signature analysis, it can be easily updated concurrently with WRITE operations. This way, changes in memory do not require a time consuming recomputation. The respective test characteristics can be efficiently computed during the periodic refresh operations of the dynamic RAM. Experiments show that the proposed technique significantly reduces the time between the occurrence of an error and its detection (error detection latency). Compared to error detecting codes (EDC) it also achieves a significantly higher error coverage at lower hardware costs. Therefore, it perfectly complements standard online checking approaches relying on EDC, where the concurrent detection of certain types of errors is guaranteed, but only during READ operations accessing the erroneous data.