Symmetric transparent BIST for RAMs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Self-adjusting output data compression: an efficient BIST technique for RAMs
Proceedings of the conference on Design, automation and test in Europe
Built-In Self-Diagnosis for Repairable Embedded RAMs
IEEE Design & Test
A Tutorial on Built-In Self-Test, Part 2: Applications
IEEE Design & Test
Efficient Online and Offline Testing of Embedded DRAMs
IEEE Transactions on Computers
Transparent Word-Oriented Memory BIST Based on Symmetric March Algorithms
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Error Detecting Refreshment for Embedded DRAMs
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Testing and Reliability Techniques for High-Bandwidth Embedded RAMs
Journal of Electronic Testing: Theory and Applications
Extending boundary-scan to perform a memory built-in self-test
ICC'05 Proceedings of the 9th International Conference on Circuits
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The authors present the specification and design of a self-test mechanism for static random-access memories (RAMs). The test algorithm provides excellent fault detection, and its structure is independent of address and data scrambling. The self-test machine generates data backgrounds on chip and is therefore suitable for both bit-oriented and word-oriented SRAMs. It is also suitable for both embedded SRAMs and stand-alone SRAMs, and adapts to boundary-scan environment. Because of the regular and symmetric structure of the test algorithm, the silicon overhead is only 3% for a 16 K synchronous SRAM.