Fundamentals of MOS digital integrated circuits
Fundamentals of MOS digital integrated circuits
Testing semiconductor memories: theory and practice
Testing semiconductor memories: theory and practice
Testing of static random access memories by monitoring dynamic power supply current
Journal of Electronic Testing: Theory and Applications
Technology and layout-related testing of static random-access memories
Journal of Electronic Testing: Theory and Applications - Special issue: on memory testing
Testing complex couplings in multiport memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Testing and testable design of high-density random-access memories
Testing and testable design of high-density random-access memories
Bisramgen: a silicon complier for built-in self-repairable random-access memories
Bisramgen: a silicon complier for built-in self-repairable random-access memories
A physical design tool for built-in self-repairable static RAMs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
New March Tests for Multiport RAM Devices
Journal of Electronic Testing: Theory and Applications
Dynamic Power Supply Current Testing of CMOS SRAMs
Journal of Electronic Testing: Theory and Applications - Special Issue on the 7th ASIAN TEST SYMPOSIUM, ATS-98
Intrinsic leakage in deep submicron CMOS ICs—measurement-based test solutions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
A physical design tool for built-in self-repairable RAMs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Realistic Built-In Self-Test for Static RAMs
IEEE Design & Test
Serial Interfacing for Embedded-Memory Testing
IEEE Design & Test
Built-In Self-Diagnosis for Repairable Embedded RAMs
IEEE Design & Test
Increasing Current Testing Resolution
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
IDDQ Test: Sensitivity Analysis of Scaling
Proceedings of the IEEE International Test Conference on Test and Design Validity
Built in self repair for embedded high density SRAM
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Semiconductor manufacturing process monitoring using built-in self-test for embedded memories
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Very-Low-Voltage Testing for Weak CMOS Logic ICs
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Proceedings of the IEEE International Test Conference 2001
EDTC '97 Proceedings of the 1997 European conference on Design and Test
False write through and un-restored write electrical level fault models for SRAMs
MTDT '97 Proceedings of the 1997 IEEE International Workshop on Memory Technology, Design and Testing
Current signatures [VLSI circuit testing]
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Disturb Neighborhood Pattern Sensitive Fault
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
6.3 Experimental Results for IDDQ and VLV Testing
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
On the Comparison of IDDQ and IDDQ Testing
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Detection and location of faults and defects using digital signal processing
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
MINVDD Testing for Weak CMOS ICs
VTS '01 Proceedings of the 19th IEEE VLSI Test Symposium
DFT Advances in Motorola's MPC7400, a PowerPCTM Microprocessor
ITC '99 Proceedings of the 1999 IEEE International Test Conference
New fault models and efficient BIST algorithms for dual-port memories
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Application-specific integrated circuits (ASICs) and high-performance processors such as Itanium and Compaq Alpha use a total of almost 75% of chip real estate for accommodating various types of embedded (or on-chip) memories. Although most of these embedded memories are single-port static (and in relatively few cases, dynamic) RAMs today, the high demand for bandwidth in digital television, fast signal processing, and high-speed networking applications will also fuel the need for on-chip multiport memories in the foreseeable future. The reliability of a complex VLSI chip will depend largely on the reliability of these embedded memory blocks. With device dimensions moving rapidly toward the ultimate physical limits of device scaling, which is in the regime of feature sizes of 50 nm or so, a host of complex failure modes is expected to occur in memory circuits. This tutorial underlines the need for appropriate testing and reliability techniques for the present to the next generation of embedded RAMs. Topics covered include: reliability and quality testing, fault modeling, advanced built-in self-test (BIST), built-in self-diagnosis (BISD), and built-in self-repair (BISR) techniques for high-bandwidth embedded RAMs.