Increasing Current Testing Resolution

Authors:
Claude Thibeault
Affiliations:
-
Venue:
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Year:
1998

Citing 0
Cited 6

On the Adaptation of Viterbi Algorithm for Diagnosis of Multiple Bridging Faults

IEEE Transactions on Computers
Diagnosis Method Using ΔIDDQ Probabilistic Signatures: Theory and Results

Journal of Electronic Testing: Theory and Applications
On the Comparison of IDDQ and IDDQ Testing

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
An Histogram Based Procedure for Current Testing of Active Defects

ITC '99 Proceedings of the 1999 IEEE International Test Conference
Testing and Reliability Techniques for High-Bandwidth Embedded RAMs

Journal of Electronic Testing: Theory and Applications
IDDX-based test methods: A survey

ACM Transactions on Design Automation of Electronic Systems (TODAES)

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Abstract

The purpose of this paper is to experimentally show that IDDQ testing has a rather poor resolution when used to estimate additional current caused by active defects, and that a significant current testing resolution can be obtained with simple data processing. We propose a methodology based on the use of two different criteria the two kinds of current defects - passive and active. This paper represents the first step and deals with active defects. Here we compare different methods applied to estimate additional current caused by this sort of defects. Using Sematech Project S121 data, we show that a resolution gain of 10 over IDDQ testing can be reached with simple data processing.