IEEE Spectrum
Algorithms for current monitor based diagnosis of bridging and leakage faults
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Diagnosis of leakage faults with IDDQ
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
Identifying defects in deep-submicron CMOS ICs
IEEE Spectrum
Test Generation for Current Testing (CMOS ICs)
IEEE Design & Test
IC Failure Analysis: Magic, Mystery, and Science
IEEE Design & Test
Increasing Current Testing Resolution
DFT '98 Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems
IDDQ Test: Sensitivity Analysis of Scaling
Proceedings of the IEEE International Test Conference on Test and Design Validity
Burn-in Elimination of a High Volume Microprocessor Using IDDQ
Proceedings of the IEEE International Test Conference on Test and Design Validity
Estimation of defect-free IDDQ in submicron circuits using switch level simulation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Diagnosis method based on /spl Delta/Iddq probabilistic signatures: experimental results
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A novel built-in current sensor for I/sub DDQ/ testing of deep submicron CMOS ICs
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
Current signatures [VLSI circuit testing]
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
On estimating bounds of the quiescent current for I/sub DDQ/ testin
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
Current Signatures for Production Testing
IDDQ '96 Proceedings of the 1996 IEEE International Workshop on IDDQ Testing (IDDQ '96)
A Simulation-Based Method for Estimating Defect-Free IDDQ
IDDQ '97 Proceedings of the 1997 IEEE International Workshop on IDDQ Testing (IDDQ '97)
IDDQ Data Analysis Using Current Signature
IDDQ '98 Proceedings of the IEEE International Workshop on IDDQ Testing
Detection and location of faults and defects using digital signal processing
VTS '95 Proceedings of the 13th IEEE VLSI Test Symposium
An Histogram Based Procedure for Current Testing of Active Defects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
On the Adaptation of Viterbi Algorithm for Diagnosis of Multiple Bridging Faults
IEEE Transactions on Computers
Diagnosis Method Using ΔIDDQ Probabilistic Signatures: Theory and Results
Journal of Electronic Testing: Theory and Applications
IC Diagnosis Using Multiple Supply Pad IDDQs
IEEE Design & Test
Replacing IDDQ Testing: With Variance Reduction
Journal of Electronic Testing: Theory and Applications
Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Test Method Evaluation Experiments & Data
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Improving Delta-IDDQ-based test methods
ITC '00 Proceedings of the 2000 IEEE International Test Conference
VARIANCE REDUCTION USING WAFER PATTERNS in IddQ DATA
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Increasing the IDDQ Test Resolution Using Current Prediction
ITC '00 Proceedings of the 2000 IEEE International Test Conference
DECOUPLE: DEFECT CURRENT DETECTION IN DEEP SUBMICRON IDDQ
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Improved Wafer-level Spatial Analysis for IDDQ Limit Setting
ITC '01 Proceedings of the 2001 IEEE International Test Conference
An Evaluation of Defect-Oriented Test: WELL-controlled Low Voltage Test
ITC '01 Proceedings of the 2001 IEEE International Test Conference
A Practical Built-In Current Sensor for IDDQ Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
An Histogram Based Procedure for Current Testing of Active Defects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IDDQ Testing in Deep Submicron Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
Testing and Reliability Techniques for High-Bandwidth Embedded RAMs
Journal of Electronic Testing: Theory and Applications
On New Current Signatures and Adaptive Test Technique Combination
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
FPGA Bridging Fault Detection and Location via Differential I{DDQ}
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Novel On-Chip Amplifier for Fast IDD Current Monitoring
Analog Integrated Circuits and Signal Processing
Defect Detection Using Quiescent Signal Analysis
Journal of Electronic Testing: Theory and Applications
Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method
IEEE Design & Test
Graphical IDDQ signatures reduce defect level and yield loss
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
CδIDDQ: improving current-based testing and diagnosis through modified test pattern generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Transactions on high-performance embedded architectures and compilers III
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The purpose of this paper is to compare differential Iddq to Iddq itself, in their capabilities of detecting active current defects/faults, as bridging faults. To perform this comparison, a mathematical framework is developed, based on assumptions validated with data from the Sematech experiment S121 1 . The comparison results reveal that the probability of false test decision can be reduced by orders of magnitude by using differential Iddq instead of Iddq. Based on the same framework, we also show that a wise vector selection may contribute to decrease by orders of magnitude the probability of a false test decision. Finally, we investigate the applicability of differential Iddq with deep-submicron technologies, by estimating the number of (pairs of) vectors required to achieve a given test quality level. The proposed framework and the results help to understand the tendencies and to identify the requirements in order to meet the challenges of deep-submicron current testing.