IDDQ Test: Sensitivity Analysis of Scaling
Proceedings of the IEEE International Test Conference on Test and Design Validity
Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs
Proceedings of the IEEE International Test Conference
Current Signatures: Application
Proceedings of the IEEE International Test Conference
Failure analysis of timing and IDDq-only failures from the SEMATECH test methods experiment
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Current signatures [VLSI circuit testing]
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
On the Comparison of IDDQ and IDDQ Testing
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Delta Iddq for Testing Reliability
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
Current Signatures for Production Testing
IDDQ '96 Proceedings of the 1996 IEEE International Workshop on IDDQ Testing (IDDQ '96)
Clustering Based Techniques for IDDQ Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
An Histogram Based Procedure for Current Testing of Active Defects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IDDQ Testing in Deep Submicron Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Replacing IDDQ Testing: With Variance Reduction
Journal of Electronic Testing: Theory and Applications
The Future of Delta IDDQ Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Journal of Electronic Testing: Theory and Applications
On New Current Signatures and Adaptive Test Technique Combination
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Defect Detection Using Quiescent Signal Analysis
Journal of Electronic Testing: Theory and Applications
Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method
IEEE Design & Test
Graphical IDDQ signatures reduce defect level and yield loss
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The Variations in IDDQ due to process disturbances forsub-micron ICs is comparable to magnitude of defectinduced currents. This is making traditional IDDQ testingineffective in detecting defects in sub-micron ICs. Thispaper presents a methodology called current predictionfor enhancing the effectiveness of IDDQ testing. In theproposed methodology, a set of IDDQ measurements areperformed on the device and the value of each IDDQcurrent are predicted using regression models. Absolutevalue of the difference between measured and predictedIDDQ (residuals of current prediction) are used foridentifying defective devices. The residuals of currentprediction are very sensitive to the defect currents and isinsensitive to process variations thus increasing the IDDQtest resolution. This technique is compared withtraditional and delta IDDQ testing techniques using theproduction test data from two different ICs. Results showthat considerable improvement in the IDDQ test qualitycan be achieved with the proposed technique.