Current Ratios: A Self-Scaling Technique for Production IDDQ Testing

Authors:
Peter Maxwell;Pete O'Neill;Rob Aitken;Roland Dudley;Neal Jaarsma;Minh Quach;Don Wiseman
Affiliations:
-;-;-;-;-;-;-
Venue:
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Year:
1999

Citing 13
Cited 45

IDDQ Test: Sensitivity Analysis of Scaling

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IDDQ Characterization in Submicron CMOS

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Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs

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Current Signatures: Application

Proceedings of the IEEE International Test Conference
Estimation of defect-free IDDQ in submicron circuits using switch level simulation

ITC '98 Proceedings of the 1998 IEEE International Test Conference
A General Purpose IDDQ Measurement Circuit

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CMOS IC reliability indicators and burn-in economics

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Diagnosis method based on /spl Delta/Iddq probabilistic signatures: experimental results

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An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing

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On the Comparison of IDDQ and IDDQ Testing

VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Current Signatures for Production Testing

IDDQ '96 Proceedings of the 1996 IEEE International Workshop on IDDQ Testing (IDDQ '96)
An Histogram Based Procedure for Current Testing of Active Defects

ITC '99 Proceedings of the 1999 IEEE International Test Conference

On effective IDDQ Testing of low-voltage CMOS circuits using leakage control techniques

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LEAP: An Accurate Defect-Free IDDQ Estimator

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Studies of the SEMATECH IDDq test data

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IC Diagnosis Using Multiple Supply Pad IDDQs

IEEE Design & Test
Current-Based Testing for Deep-Submicron VLSIs

IEEE Design & Test
IDDQ Test: Will It Survive the DSM Challenge?

IEEE Design & Test
Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits

IEEE Design & Test
Neighborhood Selection for IDDQ Outlier Screening at Wafer Sort

IEEE Design & Test
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Journal of Electronic Testing: Theory and Applications
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ETW '00 Proceedings of the IEEE European Test Workshop
Comparison of Defect Detection Capabilities of Current-Based and Voltage-Based Test Methods

ETW '00 Proceedings of the IEEE European Test Workshop
LEAP: An Accurate Defect-Free IDDQ Estimator

ETW '00 Proceedings of the IEEE European Test Workshop
Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification

VLSID '03 Proceedings of the 16th International Conference on VLSI Design
New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss

VLSID '03 Proceedings of the 16th International Conference on VLSI Design
An Analysis of the Delay Defect Detection Capability of the ECR Test Method

ITC '00 Proceedings of the 2000 IEEE International Test Conference
Multiple-Parameter CMOS IC Testing with Increased Sensitivity for IDDQ

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Test Method Evaluation Experiments & Data

ITC '00 Proceedings of the 2000 IEEE International Test Conference
An Empirical Study on the Effects of Test Type Ordering on

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Improving Delta-IDDQ-based test methods

ITC '00 Proceedings of the 2000 IEEE International Test Conference
VARIANCE REDUCTION USING WAFER PATTERNS in IddQ DATA

ITC '00 Proceedings of the 2000 IEEE International Test Conference
Increasing the IDDQ Test Resolution Using Current Prediction

ITC '00 Proceedings of the 2000 IEEE International Test Conference
DECOUPLE: DEFECT CURRENT DETECTION IN DEEP SUBMICRON IDDQ

ITC '00 Proceedings of the 2000 IEEE International Test Conference
Power Supply Transient Signal Integration Circuit

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Improved Wafer-level Spatial Analysis for IDDQ Limit Setting

ITC '01 Proceedings of the 2001 IEEE International Test Conference
The Future of Delta IDDQ Testing

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An Evaluation of Defect-Oriented Test: WELL-controlled Low Voltage Test

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NEIGHBOR SELECTION FOR VARIANCE REDUCTION IN IDDQ and OTHER PARAMETRIC DATA

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A Practical Built-In Current Sensor for IDDQ Testing

ITC '01 Proceedings of the 2001 IEEE International Test Conference
An Histogram Based Procedure for Current Testing of Active Defects

ITC '99 Proceedings of the 1999 IEEE International Test Conference
It Makes Sense to Combine DFT and DFR/DFY

ITC '99 Proceedings of the 1999 IEEE International Test Conference
Eliminating the Ouija® Board: Automatic Thresholds and Probabilistic IDDQ Diagnosis

ITC '99 Proceedings of the 1999 IEEE International Test Conference
Wafer-Package Test Mix for Optimal Defect Detection and Test Time Savings

IEEE Design & Test
Defect Diagnosis Using a Current Ratio Based Quiescent Signal Analysis Model for Commercial Power Grids

Journal of Electronic Testing: Theory and Applications
On Faster IDDQ Measurements

Journal of Electronic Testing: Theory and Applications
Multiple-parameter CMOS IC testing with increased sensitivity for IDDQ

IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
On New Current Signatures and Adaptive Test Technique Combination

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
Built-in Current Sensor for "I{DDQ} Testing of Deep Submicron Digital CMOS ICs

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
On Comparison of NCR Effectiveness with a Reduced I{DDQ} Vector Set

VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
IDDX-based test methods: A survey

ACM Transactions on Design Automation of Electronic Systems (TODAES)
IDDQ data analysis using neighbor current ratios

Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Desing and test of systems on a chip
Defect Detection Using Quiescent Signal Analysis

Journal of Electronic Testing: Theory and Applications
Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method

IEEE Design & Test
Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries

Integration, the VLSI Journal
Graphical IDDQ signatures reduce defect level and yield loss

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CδIDDQ: improving current-based testing and diagnosis through modified test pattern generation

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

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Abstract

The use of a single pass/fail threshold for IDDQtesting is unworkable as chip background currentsincrease to the point where they exceed many defectcurrents.This paper describes a method of using"current signatures" which uses only simplecomparisons on the tester, and which automaticallyscales with process variations which give a wide rangeof background currents.Dynamic thresholds are used,based on the ratio of maximum to minimum current.Using a single IDDQ measurement for each die, upperand lower comparator values are set, against whichIDDQ for each vector in the suite is compared.Production data is presented to verify the validity of themethod.