VARIANCE REDUCTION USING WAFER PATTERNS in IddQ DATA

Authors:
W. Robert Daasch;James McNames;Daniel Bockelman;Kevin Cota
Affiliations:
-;-;-;-
Venue:
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Year:
2000

Citing 8
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Abstract

The subject of this paper is IddQ testing for deep submicron CMOS technologies. The key concept introducedis the need to reduce the variance of good and faulty IddQdistributions. Other IddQ based techniques are reviewed within the context of variance reduction. Using theSEMATECH data and production data, variance reductiontechniques are demonstrated. The main contribution of thepaper is the systematic use of the die location and patternsin the IddQ data to reduce variance. Variance reduction iscompleted before any IddQ threshold limits are set.