Test Method Evaluation Experiments & Data
ITC '00 Proceedings of the 2000 IEEE International Test Conference
VARIANCE REDUCTION USING WAFER PATTERNS in IddQ DATA
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Improved Wafer-level Spatial Analysis for IDDQ Limit Setting
ITC '01 Proceedings of the 2001 IEEE International Test Conference
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Defect Detection Using Quiescent Signal Analysis
Journal of Electronic Testing: Theory and Applications
Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method
IEEE Design & Test
Graphical IDDQ signatures reduce defect level and yield loss
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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As device dimensions approach 0.1 /spl mu/m, analog effects will play an even larger role in digital circuits. IDDQ measurements can be significantly affected by the observed wafer to wafer (and even die to die) variations in electrical parameters. In this presentation we make a case for a Wafer Oriented Test Evaluation (WOTE) strategy where acceptable IDDQ thresholds are set based on the IDDQ measurements observed for the neighbouring die. Such an approach will minimize yield loss due to IDDQ testing while identifying defective die with abnormal IDDQ in comparison with their neighbours.