Test generation of stuck-open faults using stuck-at test sets in CMOS combinational circuits
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Fault Injection for Dependability Validation: A Methodology and Some Applications
IEEE Transactions on Software Engineering
Testability analysis and improvement from VHDL behavioral specifications
EURO-DAC '94 Proceedings of the conference on European design automation
FERRARI: A Flexible Software-Based Fault and Error Injection System
IEEE Transactions on Computers - Special issue on fault-tolerant computing
A Methodology for the Rapid Injection of Transient Hardware Errors
IEEE Transactions on Computers
FX: a fast approximate fault simulator for the switch-level using VHDL
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 1995 IEEE ASIC conference
A fault model for VHDL descriptions at the register transfer level
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Logic Testing of Bridging Faults in CMOS Integrated Circuits
IEEE Transactions on Computers
E-PROOFS: a CMOS bridging fault simulator
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
VHDL modelling and analysis of fault secure systems
Proceedings of the conference on Design, automation and test in Europe
A Fault Injection Technique for VHDL Behavioral-Level Models
IEEE Design & Test
Xception: A Technique for the Experimental Evaluation of Dependability in Modern Computers
IEEE Transactions on Software Engineering
Residual Charge on the Faulty Floating Gate MOS Transistor
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
Fault Coverage Analysis for Physically-Based CMOS Bridging Faults at Different Power Supply Voltages
Proceedings of the IEEE International Test Conference on Test and Design Validity
Defect-Oriented IC Test and Diagnosis Using VHDL Fault Simulation
Proceedings of the IEEE International Test Conference on Test and Design Validity
Test Pattern Generation for Realistic Bridge Faults in CMOS ICs
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
VERIFY: Evaluation of Reliability Using VHDL-Models with Embedded Fault Descriptions
FTCS '97 Proceedings of the 27th International Symposium on Fault-Tolerant Computing (FTCS '97)
Implementing A Complete Test Tool Set In VHDL
VIUF '97 Proceedings of the 1997 VHDL International User's Forum (VIUF '97)
Functional Fault Simulation of VHDL Gate Level Models
VIUF '97 Proceedings of the 1997 VHDL International User's Forum (VIUF '97)
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IC bridge fault modeling for IP blocks using neural network-based VHDL saboteurs
IEEE Transactions on Computers
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Popular generic fault models, which exhibit limited realism for different IC technologies, have been widely misused due to their simplicity and cost-effective implementation. This paper introduces a system for deriving accurate, technology specific fault models that are based on analog defect simulation. This technique, though used in other research efforts, is formally defined in this paper and a systematic approach is developed. It is supported by a new software tool that provides a push-button solution for the previously tedious task of obtaining accurate ASIC cell defect to fault mappings. Furthermore, upon completion of the cell defect analysis, the tool automatically generates VITAL compliant, defect-injectable, VHDL cell models.