A measurement-based model for workload dependence of CPU errors
IEEE Transactions on Computers - The MIT Press scientific computation series
Fault Injection Experiments Using FIAT
IEEE Transactions on Computers
On the prediction of fault behavior based on workload
On the prediction of fault behavior based on workload
Reliable computer systems (2nd ed.): design and evaluation
Reliable computer systems (2nd ed.): design and evaluation
Observations on the Effects of Fault Manifestation as a Function of Workload
IEEE Transactions on Computers - Special issue on fault-tolerant computing
The automatic generation of instruction-level error manifestations of hardware faults: a new fault-injection model
FOCUS: An Experimental Environment for Fault Sensitivity Analysis
IEEE Transactions on Computers
Xception: A Technique for the Experimental Evaluation of Dependability in Modern Computers
IEEE Transactions on Software Engineering
A Dependability-Explicit Model for the Development of Computing Systems
SAFECOMP '00 Proceedings of the 19th International Conference on Computer Safety, Reliability and Security
From Experimental Assessment of Fault-Tolerant Systems to Dependability Benchmarking
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Comparison of Physical and Software-Implemented Fault Injection Techniques
IEEE Transactions on Computers
Reflections on Industry Trends and Experimental Research in Dependability
IEEE Transactions on Dependable and Secure Computing
Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries
Integration, the VLSI Journal
| Hi-index | 14.98 |
Ultra-dependable computing demands verification of fault-tolerant mechanisms in the hardware. The most popular class of verification methodologies, fault-injection, is fraught with a host of limitations. Methods which are rapid enough to be feasible are not based on actual hardware faults. On the other hand, methods which are based on gate-level faults require enormous time resources. This research tries to bridge that gap by developing a new fault-injection methodology for processors based on a register-transfer-language (RTL) fault model. The fault model is developed by abstracting the effects of low-level faults to the RTL level. This process attempts to be independent of implementation details without sacrificing coverage, the proportion of errors generated by gate-level faults that are successfully reproduced by the RTL fault model. A prototype tool, ASPHALT, is described which automates the process of generating the error patterns. The IBM RISC-Oriented Micro-Processor (ROMP) is used as a basis for experimentation. Over 1.5 million transient faults are injected using a gate-level model. Over 97% of these are reproduced with the RTL model at a speedup factor of over 500:1. These results show that the RTL fault model may be used to greatly accelerate fault-injection experiments without sacrificing accuracy.