A measurement-based model for workload dependence of CPU errors
IEEE Transactions on Computers - The MIT Press scientific computation series
Measurement-Based Analysis of Error Latency
IEEE Transactions on Computers
On the prediction of fault behavior based on workload
On the prediction of fault behavior based on workload
The Effects of Heavy-Ion Induced Single Event Upsets in the MC6809E Microprocessor
Fehlertolerierende Rechensysteme / Fault-Tolerant Computing Systems, Automatisierungssysteme, Methoden, Anwendungen / Automation Systems, Methods, Applications; 4. Internationale GI/ITG/GMA-Fachtagung
FERRARI: A Flexible Software-Based Fault and Error Injection System
IEEE Transactions on Computers - Special issue on fault-tolerant computing
A Methodology for the Rapid Injection of Transient Hardware Errors
IEEE Transactions on Computers
Fault behavior dictionary for simulation of device-level transients
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
E-PROOFS: a CMOS bridging fault simulator
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Stress-Based and Path-Based Fault Injection
IEEE Transactions on Computers
Hierarchical Simulation Approach to Accurate Fault Modeling for System Dependability Evaluation
IEEE Transactions on Software Engineering
SEU effect analysis in an open-source router via a distributed fault injection environment
Proceedings of the conference on Design, automation and test in Europe
Computer
A Fault Injection Technique for VHDL Behavioral-Level Models
IEEE Design & Test
A Reliability Testing Environment for Off-the-Shelf Memory Subsystems
IEEE Design & Test
Xception: A Technique for the Experimental Evaluation of Dependability in Modern Computers
IEEE Transactions on Software Engineering
Can Software Implemented Fault-Injection Be Used on Real-Time Systems?
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Fault Injection into VHDL Models: Experimental Validation of a Fault Tolerant Microcomputer System
EDCC-3 Proceedings of the Third European Dependable Computing Conference on Dependable Computing
Proceedings of the 40th annual Design Automation Conference
FAMAS: FAult Modeling via Adaptive Simulation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
IOLTW '00 Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW)
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Emulating switch-level models of CMOS circuits
Microelectronic Engineering
Study of the Effects of SEU-Induced Faults on a Pipeline Protected Microprocessor
IEEE Transactions on Computers
FTCS'95 Proceedings of the Twenty-Fifth international conference on Fault-tolerant computing
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FOCUS, a simulation environment for conducting fault-sensitivity analysis of chip-level designs, is described. The environment can be used to evaluate alternative design tactics at an early design stage. A range of user specified faults is automatically injected at runtime, and their propagation to the chip I/O pins is measured through the gate and higher levels. A number of techniques for fault-sensitivity analysis are proposed and implemented in the FOCUS environment. These include transient impact assessment on latch, pin and functional errors, external pin error distribution due to in-chip transients, charge-level sensitivity analysis, and error propagation models to depict the dynamic behavior of latch errors. A case study of the impact of transient faults on microprocessor-based jet-engine controller is used to identify the critical fault propagation paths, the module most sensitive to fault propagation, and the module with the highest potential for causing external errors.