Error diagnosis for transistor-level verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
Efficient modeling of switch-level networks containing undetermined logic node states
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A switch level fault simulation environment
Proceedings of the 37th Annual Design Automation Conference
Automated equivalence checking of switch level circuits
Proceedings of the 39th annual Design Automation Conference
FOCUS: An Experimental Environment for Fault Sensitivity Analysis
IEEE Transactions on Computers
Logic Verification of Very Large Circuits Using Shark
VLSID '99 Proceedings of the 12th International Conference on VLSI Design - 'VLSI for the Information Appliance'
Functional abstraction of logic gates for switch-level simulation
EURO-DAC '91 Proceedings of the conference on European design automation
Fault emulation: A new methodology for fault grading
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CMOS circuit verification with symbolic switch-level timing simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Emulating switch-level models of CMOS circuits
Microelectronic Engineering
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This paper presents a method for the fast emulation of switch-level circuits using FPGAs. In this method, logic gates are used to model switch-level circuits without any abstraction. In contrast to the abstraction methods for which transistors are grouped together to form gates, in this method, gates are grouped together to form the switch models of transistors. Unlike the abstraction methods, the method presented in this paper can emulate many important features of switch-level models, such as bi-directional signal propagation and variations in driving strength. In order to attain a better utilization of FPGA resources a mixed-mode emulation approach has been used. In this approach parts of the circuit are emulated at the switch-level while the rest of the circuit is emulated at the gate-level.