CMOS circuit verification with symbolic switch-level timing simulation

Authors:
C. B. McDonald;R. E. Bryant
Affiliations:
Dept. of Electr. & Comput. Eng., Carnegie Mellon Univ., Pittsburgh, PA;-
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2006

Citing 0
Cited 4

A symbolic simulation-based methodology for generating black-box timing models of custom macrocells

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Switch-level emulation

Proceedings of the 40th annual Design Automation Conference
A formal framework for verification of embedded custom memories of the Motorola MPC7450 microprocessor

Formal Methods in System Design
Emulating switch-level models of CMOS circuits

Microelectronic Engineering

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Abstract

Symbolic switch-level simulation has been extensively applied to the functional verification of complementary metal-oxide-semiconductor (CMOS) circuitry. We have extended this technique to account for real-valued data-dependent delay values and have developed a novel mechanism for symbolically computing data-dependent Elmore delays. We present our symbolic simulation and delay calculation algorithms and discuss their application to the timing and functional verification of full-custom transistor-level CMOS circuitry