Functional timing analysis for IP characterization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Computing logic-stage delays using circuit simulation and symbolic elmore analysis
Proceedings of the 38th annual Design Automation Conference
Symbolic functional and timing verification of transistor-level circuits
Symbolic functional and timing verification of transistor-level circuits
CMOS circuit verification with symbolic switch-level timing simulation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Timing model extraction of hierarchical blocks by graph reduction
Proceedings of the 39th annual Design Automation Conference
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We present a methodology for generating black-box timing models for full-custom transistor-level CMOS circuits. Our approach utilizes transistor-level ternary symbolic timing simulation to explore the input arrival time space and determine the input arrival time windows that result in proper operation. This approach integrates symbolic timing simulation into existing static timing analysis flows and allows automated modelling of the timing behavior of aggressive full-custom circuit design styles.