Automatic generation of behavioral models from switch-level descriptions
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
LOGEX—an automatic logic extractor form transistor to gate level for CMOS technology
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
DESB, a functional abstractor for CMOS VLSI circuits
EURO-DAC '92 Proceedings of the conference on European design automation
Error diagnosis for transistor-level verification
DAC '94 Proceedings of the 31st annual Design Automation Conference
Verity—a formal verification program for custom CMOS circuits
IBM Journal of Research and Development - Special issue: IBM CMOS technology
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Proceedings of the 40th annual Design Automation Conference
Extraction error modeling and automated model debugging in high-performance custom designs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Switch-level simulation has become a common means for accurate modeling of MOS circuit behavior. In this paper, we propose a new method for detecting logic gate implementations and accurately modeling their switch-level behavior. The functional abstraction replaces logic gate implementation in the switch-level description with an accurate high-level model which incorporates all relevant switch-level phenomena. The switch-level accuracy of the simulation is, therefore, preserved. However, since the gate implementations are modeled at a higher, more abstract level, the simulation speed is greatly increased. The functional abstraction is automatic and completely transparent to the user. Detection of a gate is determined by expressing the logic function of a transistor network in the sum-of-product notation and is not limited to a specific design style. The proposed algorithms have been implemented and tested on several large circuits, including a complete microprocessor. For this processor, 85% of all transistors were substituted with high-level models. A significant decrease in simulation time and storage requirement occurred for these circuits when gate abstraction was performed.