COSMOS: a compiled simulator for MOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
VLSI design parsing (preliminary version)
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
NETHDL: abstraction of schematics to high-level HDL
EURO-DAC '90 Proceedings of the conference on European design automation
Derivation of signal flow for switch-level simulation
EURO-DAC '90 Proceedings of the conference on European design automation
Functional abstraction of logic gates for switch-level simulation
EURO-DAC '91 Proceedings of the conference on European design automation
The simulation automation system (SAS); concepts, implementation, and results
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Applications of Boolean Satisfiability to Verification and Testing of Switch-Level Circuits
Journal of Electronic Testing: Theory and Applications
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This paper discusses the automatic generation of high-level software models from switch-level circuit descriptions. The proposed algorithms operate directly on the hierarchical description, and incorporate information about the design such as the structure, regularity, functionality, and control signals in the generation process. New algorithms are proposed and have been implemented for combinational modules and bus structures. A significant speedup has been obtained for these modules of a commercially available chip.