A prototype of a VHDL-based fault injection tool: description and application
Journal of Systems Architecture: the EUROMICRO Journal - Defect and fault tolerance in VLSI Systems
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EDCC-4 Proceedings of the 4th European Dependable Computing Conference on Dependable Computing
GOOFI: Generic Object-Oriented Fault Injection Tool
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
SystemC
Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries
Integration, the VLSI Journal
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Proceedings of the 2007 workshop on Engineering fault tolerant systems
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MODIFI: a MODel-implemented fault injection tool
SAFECOMP'10 Proceedings of the 29th international conference on Computer safety, reliability, and security
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ISPDC'03 Proceedings of the Second international conference on Parallel and distributed computing
FAST: An RTL Fault Simulation Framework based on RTL-to-TLM Abstraction
Journal of Electronic Testing: Theory and Applications
SEU Fault-Injection in VHDL-Based Processors: A Case Study
Journal of Electronic Testing: Theory and Applications
Combining Fault-Injection with Property-Based Testing
Proceedings of International Workshop on Engineering Simulations for Cyber-Physical Systems
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A new technique for reliability evaluation of digital systems will be presented by demonstrating the functionality and usage of the simulation based fault injector VERIFY (VHDL-based Evaluation of Reliability by Injecting Faults efficientlY). This software tool introduces a new way for describing the behavior of hardware components in case of faults by extending the VHDL language with fault injection signals together with their rate of occurrence. The accuracy of the results is obtained by using the same VHDL-models which have been developed during conventional phases of hardware design. For demonstrating the capabilities of VERIFY, a VHDL-model of a simple 32-bit processor (DP32) will be used as an example to illustrate the several steps of reliability evaluation.