Design & analysis of fault tolerant digital systems
Design & analysis of fault tolerant digital systems
Fault Injection for Dependability Validation: A Methodology and Some Applications
IEEE Transactions on Software Engineering
Fault-tolerant computer system design
Fault-tolerant computer system design
Efficient modeling of switch-level networks containing undetermined logic node states
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A switch level fault simulation environment
Proceedings of the 37th Annual Design Automation Conference
VERILOG Digital System Design: Analysis and Design of Digital Systems with Cdrom
VERILOG Digital System Design: Analysis and Design of Digital Systems with Cdrom
Xception: A Technique for the Experimental Evaluation of Dependability in Modern Computers
IEEE Transactions on Software Engineering
RIFLE: A General Purpose Pin-level Fault Injector
EDCC-1 Proceedings of the First European Dependable Computing Conference on Dependable Computing
A Simulation-Based Study of a Triple Modular Redundant System Using DEFEND
Proceedings of the 5th International GI/ITG/GMA Conference on Fault-Tolerant Computing Systems, Tests, Diagnosis, Fault Treatment
MAFALDA-RT: A Tool for Dependability Assassment of Real-Time Systems
DSN '02 Proceedings of the 2002 International Conference on Dependable Systems and Networks
On the Emulation of Software Faults by Software Fault Injection
DSN '00 Proceedings of the 2000 International Conference on Dependable Systems and Networks (formerly FTCS-30 and DCCA-8)
GOOFI: Generic Object-Oriented Fault Injection Tool
DSN '01 Proceedings of the 2001 International Conference on Dependable Systems and Networks (formerly: FTCS)
VERIFY: Evaluation of Reliability Using VHDL-Models with Embedded Fault Descriptions
FTCS '97 Proceedings of the 27th International Symposium on Fault-Tolerant Computing (FTCS '97)
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
A Switch-Level Model and Simulator for MOS Digital Systems
IEEE Transactions on Computers
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This paper presents transient and permanent fault injection into Verilog models of digital systems during the design phase by a developed simulation-based fault injection tool called INJECT. With this fault injection tool, it is possible to inject crucial fault models in all abstraction levels (such as swith-level) supported by Verilog HDL. Several fault models for injecting into Verilog models are specified and described. Analyzing the results obtained from the fault injections, using INJECT enables system designers to inform from dependable parameters, such as fault latency, propagation and coverage. As a case study, a 32-bit processor, namely DP32, has been evaluated and effects of faults on some important observation points have been presented. In this study, recovered errors are distinguished from those that affected the system behavior. The errors that lead to wrong results are separated from those that do not affect the correct results.