IDDQ Test: Sensitivity Analysis of Scaling
Proceedings of the IEEE International Test Conference on Test and Design Validity
IDDQ and AC Scan: The War Against Unmodelled Defects
Proceedings of the IEEE International Test Conference on Test and Design Validity
IDDQ Characterization in Submicron CMOS
Proceedings of the IEEE International Test Conference
So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment
Proceedings of the IEEE International Test Conference
Current signatures [VLSI circuit testing]
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
A Simulation-Based Method for Estimating Defect-Free IDDQ
IDDQ '97 Proceedings of the 1997 IEEE International Workshop on IDDQ Testing (IDDQ '97)
A Switch-Level Model and Simulator for MOS Digital Systems
IEEE Transactions on Computers
LEAP: An Accurate Defect-Free IDDQ Estimator
Journal of Electronic Testing: Theory and Applications
Studies of the SEMATECH IDDq test data
Journal of Systems Architecture: the EUROMICRO Journal - Defect and fault tolerance in VLSI Systems
IDDQ Test: Will It Survive the DSM Challenge?
IEEE Design & Test
LEAP: An Accurate Defect-Free IDDQ Estimator
ETW '00 Proceedings of the IEEE European Test Workshop
Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
On the Comparison of IDDQ and IDDQ Testing
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '00 Proceedings of the 2000 IEEE International Test Conference
DECOUPLE: DEFECT CURRENT DETECTION IN DEEP SUBMICRON IDDQ
ITC '00 Proceedings of the 2000 IEEE International Test Conference
Improved Wafer-level Spatial Analysis for IDDQ Limit Setting
ITC '01 Proceedings of the 2001 IEEE International Test Conference
The Future of Delta IDDQ Testing
ITC '01 Proceedings of the 2001 IEEE International Test Conference
An Histogram Based Procedure for Current Testing of Active Defects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IDDQ Testing in Deep Submicron Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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This paper presents a switch-level simulation-basedmethod for estimating quiescent current values. Thesimulator identifies transistors that are in the proper stateto experience leakage mechanisms. This information iscombined with data about both the size of thesetransistors and various process parameters in order tocalculate the actual I DDQ value. SPICE simulationresults are presented on a variety of circuits to bothcalibrate the simulator, and to demonstrate state, time andsequence dependencies of circuits. Some preliminaryresults are also given for an actual production chip.