Deep Submicron CMOS Current IC Testing: Is There a Future?
IEEE Design & Test
Defect Classes - An Overdue Paradigm for CMOS IC
Proceedings of the IEEE International Test Conference on TEST: The Next 25 Years
High Resolution IDDQ Characterization and Testing - Practical Issues
Proceedings of the IEEE International Test Conference on Test and Design Validity
Deep Sub-micron IDDQ Test Options
Proceedings of the IEEE International Test Conference on Test and Design Validity
Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs
Proceedings of the IEEE International Test Conference
Application and Analysis of IDDQ Diagnostic Software
Proceedings of the IEEE International Test Conference
Estimation of defect-free IDDQ in submicron circuits using switch level simulation
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Toward understanding "Iddq-only" fails
ITC '98 Proceedings of the 1998 IEEE International Test Conference
A Comparison of Stuck-At Fault Coverage and IDDQ Testing on Defect Levels
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Defect level prediction for I_DDQ testing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Current signatures [VLSI circuit testing]
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
On estimating bounds of the quiescent current for I/sub DDQ/ testin
VTS '96 Proceedings of the 14th IEEE VLSI Test Symposium
On the Comparison of IDDQ and IDDQ Testing
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
Reliabilty, Test, and IDDQ Measurements
IDDQ '97 Proceedings of the 1997 IEEE International Workshop on IDDQ Testing (IDDQ '97)
Clustering Based Techniques for IDDQ Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IDDQ Testing in Deep Submicron Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Models and algorithms for bounds on leakage in CMOS circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Replacing IDDQ Testing: With Variance Reduction
Journal of Electronic Testing: Theory and Applications
Journal of Electronic Testing: Theory and Applications
On New Current Signatures and Adaptive Test Technique Combination
VTS '04 Proceedings of the 22nd IEEE VLSI Test Symposium
IDDX-based test methods: A survey
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Graphical IDDQ signatures reduce defect level and yield loss
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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IDDQ test concept for deep submicron (DSM) devices named DECOUPLE (Defect Current Observation Under the Proportion of intrinsic Leakage currents) is proposed.A new clustering method obtained two defect free groups from a production data set by abstracting from a signatureof intrinsic leakage current that is independent of processvariations. Possible pass/fail tests, diagnosis, and detection ofparametric defect currents are discussed on the data set. Anotherexample of the pass/fail tests on a second product ispresented.