Scaling of MOS technology to submicrometer feature sizes
Analog Integrated Circuits and Signal Processing - Joint special issue on analog VLSI computation
IDDQ Test: Sensitivity Analysis of Scaling
Proceedings of the IEEE International Test Conference on Test and Design Validity
Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs
Proceedings of the IEEE International Test Conference
So What Is an Optimal Test Mix? A Discussion of the SEMATECH Methods Experiment
Proceedings of the IEEE International Test Conference
Current Signatures: Application
Proceedings of the IEEE International Test Conference
High volume microprocessor test escapes, an analysis of defects our tests are missing
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Defect detection with transient current testing and its potential for deep sub-micron CMOS ICs
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Deep Sub-Micron IDDQ Testing: Issues and Solutions
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Multiple-Parameter CMOS IC Testing with Increased Sensitivity for IDDQ
ITC '00 Proceedings of the 2000 IEEE International Test Conference
ICCQ: A Test Method for Analogue VLSI Base On Current Monitoring
IDDQ '97 Proceedings of the 1997 IEEE International Workshop on IDDQ Testing (IDDQ '97)
An Histogram Based Procedure for Current Testing of Active Defects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Current Ratios: A Self-Scaling Technique for Production IDDQ Testing
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IDDQ Testing in Deep Submicron Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Transient Current Testing of 0.25 µm CMOS Devices
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Leakage Current in Sub-Quarter Micron MOSFET: A Perspective on Stressed Delta IDDQ Testing
Journal of Electronic Testing: Theory and Applications
New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
An Evaluation of Defect-Oriented Test: WELL-controlled Low Voltage Test
ITC '01 Proceedings of the 2001 IEEE International Test Conference
DFT for Delay Fault Testing of High-Performance Digital Circuits
IEEE Design & Test
Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Graphical IDDQ signatures reduce defect level and yield loss
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Current-based testing for deep-submicron VLSIs is important because of transistor sensitivity to defects as technology scales. However, unabated increases in leakage current in CMOS devices can make this testing very difficult. This article offers several solutions to this challenging problem