Introduction to IDDQ testing
Intrinsic leakage in deep submicron CMOS ICs—measurement-based test solutions
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
MOSFET Models for VLSI Circuit Simulation: Theory and Practice
MOSFET Models for VLSI Circuit Simulation: Theory and Practice
Current-Based Testing for Deep-Submicron VLSIs
IEEE Design & Test
The future of delta I_DDQ testing
Proceedings of the IEEE International Test Conference 2001
IDDQ Test: Sensitivity Analysis of Scaling
Proceedings of the IEEE International Test Conference on Test and Design Validity
Intrinsic Leakage in Low-Power Deep Submicron CMOS ICs
Proceedings of the IEEE International Test Conference
Current Signatures: Application
Proceedings of the IEEE International Test Conference
CMOS IC reliability indicators and burn-in economics
ITC '98 Proceedings of the 1998 IEEE International Test Conference
IDDQ Defect Detection in Deep Submicron CMOS ICs
ATS '98 Proceedings of the 7th Asian Test Symposium
Current Testing Procedure for Deep Submicron Devices
ETW '00 Proceedings of the IEEE European Test Workshop
Delta Iddq for Testing Reliability
VTS '00 Proceedings of the 18th IEEE VLSI Test Symposium
IDDQ Testing for Submicron CMOS IC Technology Qualification
IDDQ '97 Proceedings of the 1997 IEEE International Workshop on IDDQ Testing (IDDQ '97)
An Histogram Based Procedure for Current Testing of Active Defects
ITC '99 Proceedings of the 1999 IEEE International Test Conference
IDDQ Testing in Deep Submicron Integrated Circuits
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Analysis and Design of LVTSCR-based EOS/ESD Protection Circuits for Burn-in Environment
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Analog Integrated Circuits and Signal Processing
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The effectiveness of single threshold IDDQ measurement for defect detection is eroded owing to higher and more variable background leakage current in modern VLSIs. Delta IDDQ is identified as one alternative for deep submicron current measurements. Often delta IDDQ is coupled with voltage and thermal stress in order to accelerate the failure mechanisms. A major concern is the IDDQ limit setting under normal and stressed conditions. In this article, we investigate the impact of voltage and thermal stress on the background leakage. We calculate IDDQ limits for normal and stressed operating conditions of 0.18 μm n-MOSFETs using a device simulator. Intrinsic leakage current components of transistor are analyzed and the impact of technology scaling on effectiveness of stressed ΔIDDQ testing is also investigated.