Register allocation and binding for low power
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Low energy memory and register allocation using network flow
DAC '97 Proceedings of the 34th annual Design Automation Conference
Code placement techniques for cache miss rate reduction
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
IDDQ testing: state of the art and future trends
Integration, the VLSI Journal - Special issue on VLSI testing
Selective cache ways: on-demand cache resource allocation
Proceedings of the 32nd annual ACM/IEEE international symposium on Microarchitecture
Low power and high performance design challenges in future technologies
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Gated-Vdd: a circuit technique to reduce leakage in deep-submicron cache memories
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
Instruction scheduling for power reduction in processor-based system design
Proceedings of the conference on Design, automation and test in Europe
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Cache decay: exploiting generational behavior to reduce cache leakage power
ISCA '01 Proceedings of the 28th annual international symposium on Computer architecture
Drowsy caches: simple techniques for reducing leakage power
ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
On the Effect of ISSQ Testing in Reducing Early Failure Rate
Proceedings of the IEEE International Test Conference on Driving Down the Cost of Test
A General Purpose IDDQ Measurement Circuit
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
CCII+ Current Conveyor Based BIC Monitor for IDDQ Testing of Complex CMOS Circuits
EDTC '97 Proceedings of the 1997 European conference on Design and Test
On the Comparison of IDDQ and IDDQ Testing
VTS '99 Proceedings of the 1999 17TH IEEE VLSI Test Symposium
100MHz IDDQ Sensor Design with 1(A Resolution for BIST Applications
IDDQ '98 Proceedings of the IEEE International Workshop on IDDQ Testing
Assigning Program and Data Objects to Scratchpad for Energy Reduction
Proceedings of the conference on Design, automation and test in Europe
Low-leakage asymmetric-cell SRAM
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Leakage current reduction in CMOS VLSI circuits by input vector control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Challenges in Embedded Memory Design and Test
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
A process-tolerant cache architecture for improved yield in nanoscale technologies
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing data cache leakage energy using a compiler-based approach
ACM Transactions on Embedded Computing Systems (TECS)
A case for asymmetric-cell cache memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Statistical analysis of SRAM cell stability
Proceedings of the 43rd annual Design Automation Conference
Leakage-aware intraprogram voltage scaling for embedded processors
Proceedings of the 43rd annual Design Automation Conference
An IC manufacturing yield model considering intra-die variations
Proceedings of the 43rd annual Design Automation Conference
Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM
Proceedings of the 43rd annual Design Automation Conference
Process variation aware cache leakage management
Proceedings of the 2006 international symposium on Low power electronics and design
HiPEAC'08 Proceedings of the 3rd international conference on High performance embedded architectures and compilers
Cache-Aware Scratchpad-Allocation Algorithms for Energy-Constrained Embedded Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Within-die process variation is increasing in nanometer-scale process technologies. We observe that the same SRAM cell leaks differently under within-die process variations when storing 0 compared to 1; this difference can be up to 3 orders of magnitude at 60mV variation of threshold voltage (Vth). Thus, leakage can be reduced if most often the values that dissipate less leakage are stored in the cache SRAM cells. We take advantage of this fact to reduce instruction-cache leakage by presenting three binary-optimization and software-level techniques: we (i) reorder instructions within basic-blocks so that their bits better match the less-leaky state of their corresponding cache cells, (ii) statically change the register operands of the instructions with the same aim, and (iii) at boot time, initialize unused cache-lines to their corresponding least-leaky values. Experimental results show up to 54%, averaging 35%, leakage energy reduction at 60mV variation in Vth, and show that with technology scaling, this saving can reach up to 84% at 100mV Vth variation. Since our techniques are one-off and do not affect instruction cache hit ratio, this reduction is provided with only a negligible penalty, in rare cases, in data cache.