Compilers: principles, techniques, and tools
Compilers: principles, techniques, and tools
The SPARC architecture manual: version 8
The SPARC architecture manual: version 8
Power analysis of embedded software: a first step towards software power minimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
Code optimization techniques for embedded DSP microprocessors
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
1995 high level synthesis design repository
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Power analysis and minimization techniques for embedded DSP software
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computer architecture (2nd ed.): a quantitative approach
Computer architecture (2nd ed.): a quantitative approach
Optimal Code Placement of Embedded Software for Instruction Caches
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Reducing Address Bus Transitions for Low Power Memory Mapping
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Energy-efficient design of battery-powered embedded systems
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
System-level power optimization: techniques and tools
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
System-level power optimization: techniques and tools
ACM Transactions on Design Automation of Electronic Systems (TODAES)
New directions in compiler technology for embedded systems (embedded tutorial)
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Source code optimization and profiling of energy consumption in embedded systems
ISSS '00 Proceedings of the 13th international symposium on System synthesis
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 7th annual IEEE/ACM International Symposium on Code Generation and Optimization
Automating energy optimization with features
FOSD '10 Proceedings of the 2nd International Workshop on Feature-Oriented Software Development
Transactions on high-performance embedded architectures and compilers III
Energy- and performance-aware scheduling of tasks on parallel and distributed systems
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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This paper propose an instruction scheduling technique to reduce power consumed for off-chip driving. The technique minimizes the switching activity of a data bus between an on-chip cache and a main memory when instruction cache misses occur. The scheduling problem is formulated and a scheduling algorithm is also presented. Experimental results demonstrate the effectiveness and the efficiency of the proposed algorithm.