Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM

Authors:
Swaroop Ghosh;Saibal Mukhopadhyay;Keejong Kim;Kaushik Roy
Affiliations:
Purdue University, IN;Purdue University, IN;Purdue University, IN;Purdue University, IN
Venue:
Proceedings of the 43rd annual Design Automation Conference
Year:
2006

Citing 5
Cited 2

Fundamentals of modern VLSI devices

Fundamentals of modern VLSI devices
Drowsy caches: simple techniques for reducing leakage power

ISCA '02 Proceedings of the 29th annual international symposium on Computer architecture
SRAM Leakage Suppression by Minimizing Standby Supply Voltage

ISQED '04 Proceedings of the 5th International Symposium on Quality Electronic Design
Parametric yield estimation considering leakage variability

Proceedings of the 41st annual Design Automation Conference
Statistical design and optimization of SRAM cell for yield enhancement

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design

A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM

ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Software-level instruction-cache leakage reduction using value-dependence of SRAM leakage in nanometer technologies

Transactions on high-performance embedded architectures and compilers III

Quantified Score

Hi-index	0.01

Visualization

Abstract

Increasing source voltage (Source-Biasing) is an efficient technique for reducing gate and sub-threshold leakage of SRAM arrays. However, due to process variation, a higher source voltage can significantly increase data flipping in standby mode (Hold Failures) resulting in faulty memories. This imposes serious concerns in reducing standby power with source-bias. In this paper, we analyze the effect of source bias on hold failures under both inter-die and intra-die variations. We propose a self-calibrating SRAM for aggressively reducing leakage while maintaining the hold failures under control.