Design Considerations for Ultra-Low Energy Wireless Microsensor Nodes
IEEE Transactions on Computers
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
A Feasibility Study of Subthreshold SRAM Across Technology Generations
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Low-leakage SRAM Design with Dual V_t Transistors
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
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Self-calibration technique for reduction of hold failures in low-power nano-scaled SRAM
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Proceedings of the 17th ACM Great Lakes symposium on VLSI
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Proceedings of the 17th ACM Great Lakes symposium on VLSI
A 160 mV, fully differential, robust schmitt trigger based sub-threshold SRAM
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Techniques for leakage energy reduction in deep submicrometer cache memories
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Results on leakage power management in scratchpad-based embedded systems
CSS '07 Proceedings of the Fifth IASTED International Conference on Circuits, Signals and Systems
Impact of voltage scaling on nanoscale SRAM reliability
Proceedings of the Conference on Design, Automation and Test in Europe
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IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Two fast methods for estimating the minimum standby supply voltage for large SRAMs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An enhanced canary-based system with BIST for SRAM standby power reduction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of Resistive Open Defects in Drowsy SRAM Cells
Journal of Electronic Testing: Theory and Applications
Leakage-aware redundancy for reliable sub-threshold memories
Proceedings of the 48th Design Automation Conference
Unequal-error-protection codes in SRAMs for mobile multimedia applications
Proceedings of the International Conference on Computer-Aided Design
Static noise margin analysis of sub-threshold SRAM cells in deep sub-micron technology
PATMOS'05 Proceedings of the 15th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
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Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
TAP: token-based adaptive power gating
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Design space exploration of workload-specific last-level caches
Proceedings of the 2012 ACM/IEEE international symposium on Low power electronics and design
Security'12 Proceedings of the 21st USENIX conference on Security symposium
DRV-Fingerprinting: using data retention voltage of SRAM cells for chip identification
RFIDSec'12 Proceedings of the 8th international conference on Radio Frequency Identification: security and privacy issues
Stability and yield-oriented ultra-low-power embedded 6T SRAM cell design optimization
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
MAPG: memory access power gating
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Single-ended, robust 8T SRAM cell for low-voltage operation
Microelectronics Journal
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Suppressing the leakage current in memories is critical in low-power design. By reducing the standby supply voltage (VDD) to its limit, which is the Data Retention Voltage (DRV), leakage power can be substantially reduced. This paper explores how low DRV can be in a standard low leakage SRAM module and analyzes how DRV is affected by parameters such as process variations, chip temperature, and transistor sizing. An analytical model for DRV as a function of process and design parameters is presented, and forms the base for further design space explorations. This model is verified using simulations as well as measurements from a4KB SRAM chip in a 0.13µm technology. It is demonstrated that an SRAM cell state can be preserved at sub-300mV standby VDD, with more than 90% leakage power savings.