Two fast methods for estimating the minimum standby supply voltage for large SRAMs

Authors:
Jiajing Wang;Amith Singhee;Rob A. Rutenbar;Benton H. Calhoun
Affiliations:
Advanced Design Group, Intel Corporation, Hillsboro, OR;IBM T. J. Watson Research Center, Yorktown Heights, NY;University of Illinois at Urbana-Champaign, Urbana, IL;Department of Electrical and Computer Engineering, University of Virginia, Charlottesville, VA
Venue:
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Year:
2010

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Abstract

The data retention voltage (DRV) defines the minimum supply voltage for an SRAM cell to hold its state. Intra-die variation causes a statistical distribution of DRV for individual cells in a memory array. We present two fast and accurate methods to estimate the tail of the DRV distribution. The first method uses a new analytical model based on the relationship between DRV and static noise margin. The second method extends the statistical blockade technique to a recursive formulation. It uses conditional sampling for rapid statistical simulation and fits the results to a generalized Pareto distribution (GPD) model. Both the analytical DRV model and the generic GPD model show a good match with Monte Carlo simulation results and offer speedups of up to four or five orders of magnitude over Monte Carlo at the 6σ point. In addition, the two models show a very close agreement with each other at the tail up to 8σ. For error within 5% with a confidence of 95%, the analytical DRV model and the GPD model can predict DRV quantiles out to 8σ and 6.6σ respectively; and for the mean of the estimate, both models offer within 1% error relative to Monte Carlo at the 4σ point.